View AN1089_1888717.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

introduction pfc preregulators based on the boost topology working in transition mode (tm, see fig. 1) have been widespread in electronic lamp ballast systems. this kind of equipment almost always works under a sin- gle mains supply (110 or 220 vac, with some tolerance) and the use of a pfc preregulator is mainly aimed at optimising the downstream half-bridge lamp driver and improving their inherent extremely poor pf. the pfc preregulator sees the downstream stage as a constant load, so it is requested to work under a limited range of operating conditions. from the control loop standpoint, this means that the frequency compensation of the error amplifier can be very simple, typically just a feedback capacitor. its capaci- tance will be high enough to ensure the crossover frequency of the open loop gain is low, so as to achieve a high pf (see ref. [1]). march 2000 ? AN1089 application note control loop modeling of l6561-based tm pfc by claudio adragna this paper provides a model and a tool for evaluating and improving the control loop characteristics of l6561-based pfc preregulators in boost topology and operated in transition mode (tm). such a subject is now becoming topical since tm pfc preregulators are more and more used in sys- tems other than electronic lamp ballast where the input voltage range is limited and the load current is almost constant. the ability to operate under large variations of both input voltage and load current, as well as the use of tm pfc systems as preregulators for switching converters, requires a more accurate design of the control loop. the goal will be not only to ensure a narrow bandwidth in order to achieve a high power factor, but also to have enough phase margin so as to make sure the system is stable over a large range of operating conditions. 8 3 r9 r10 va c 5 6 l6561 7 21 r7 co rs r8 + - 4 vcc vo compensation network figure 1. typical l6561-based tm pfc preregulator 1/12
things get more complicated when an electronic ballast can supply two lamps and is required to work even if one lamp is not used or is exhausted, so that it is expected to work at half load as well. the l6561, thanks to its highly linear, wide dynamics multiplier, extends the use of tm pfc boost pre- regulators to applications that experience a wide range of operating conditions, both in terms of input voltage variations and load change. high power (60 to70 w) ac-dc adapters for portable equipment and computer monitor smps are the most noticeable examples. this, however, calls for a more accurate design of the control loop than the one illustrated in ref.[1]. the control goal will no longer be to achieve only a low crossover frequency but also an adequate phase margin. besides ensuring stability over a large variety of operating conditions, this is necessary to pre- vent dangerous oscillations of the output voltage as a result of load changes. pfc boost preregulator control loop to the aim of finding a compensation network able to achieve the above mentioned control goal, it is necessary to get an insight into the control loop of such systems. this can be synthesised as shown in the block diagram of fig. 2. virms error amplifier g1(s) multiplier g2 pwm modulator power stage g4(s) feedback h g3 + - + - zcd vref vo v comp v cspk i lpk figure 2. control loop of a pfc preregulator: block diagram - + driver - + pwm comparator rs e/a vref (2.5v) l6561 vo v ref l d co 7 1 2 4 q 3 r q 5 s multiplier zcd starter e/a compensation network inv comp mult cs zcd gd g4(s) g3 h g1(s) g2 k p vi v cs vi v comp r7 r8 r9 r10 v cs figure 3. control loop of a pfc preregulator: electrical circuit and main quantities AN1089 application note 2/12
fig. 3 illustrates how the various blocks of fig. 2 relate with the electrical circuit, both external and inside the l6561. for details on the internal circuit and its operation please refer to ref. [1]. the loop gain of pfc preregulators must have a very low crossover frequency (fc) so as to maintain v comp (error amplifier output) fairly constant over a given line cycle and ensure a high pf. as a rule of thumb, fc should not exceed 20-25 hz at maximum mains voltage. this allows to assume that the control action takes place on the peak amplitude (or, which is the same, the rms value) of the various quantities inside the loop. the first step is to determine the transfer function of the power stage, g4(s), defined as: g4 ( s ) = dv o di lpk = dv o di o di o di lpk where vo is the dc output voltage, io the dc output current and i lpk is the peak value of the inductor cur- rent. under the above assumption, the power stage can be modeled as illustrated in fig. 4: a controlled cur- rent source (with a shunt resistor re) that drives the output bulk capacitor co and the load resistance ro (= vo / io). the zero due to the esr associated with co is far beyond the crossover frequency thus it is neglected. the current source can be characterised with the fol- lowing considerations: the low frequency component of the boost diode current is found by averaging the discharge portion of the inductor current (the white triangles of fig. 5) over a given switching cycle. the low frequency current, averaged over a mains half-cycle yields the dc output current io: i o = 1 2 ( 1 - d ) i lpk sin q _________________ = 1 2 ? ` ` 2 v irms sin q i lpk sin q _________________________ v o = ? ` 2 4 v irms i lpk v o where d is the switch duty cycle, q is the in- stantaneous phase angle of the mains volt- age and v irms its effective (rms) value. the ac model illustrated in fig. 4 can be found by calculating the total differential of the above expression of io. a few algebraic manipulations would show that the shunt re- sistor re always equals the dc load resis- tance ro, thus it changes depending on the power delivered by the system. now it is necessary to consider two separate cases. if the load is purely resistive (or equivalent to a resistor, like in the case of a lamp ballast circuit), the ac load resistance equals ro. the parallel of this resistance with re, com- bined with the output bulk capacitor, gives origin to a pole located at: w p = 2 r o c o which is usually in the range of 1 to 5 hz. co ro re io vo figure 4. power stage model,g4(s) inductor current peak envelope low frequency diode current on off switch diode current switch current i lpk io figure 5. boost pfc currents AN1089 application note 3/12
in case the pfc preregulator provides a dc bus supplying a downstream switching converter, the load should be regarded as a "constant power" load rather than a resistor. in fact, as long as a switching con- verter is in regulation, the power it demands of the source is practically independent of the input voltage (converters efficiency changes very little). in this case, the ac load resistance is equal to -ro (if the dc bus decreases the current demanded of the pfc increases, whence the negative sign). as a result, the parallel combination with re tends to in- finity and the two resistances cancel. the current source drives only the output capacitor and the pole lo- cation tends to zero. in the end, g4(s) will be given by: g4 ( s ) = ? ? ? ? ? ? ` ` 2 8 v irms v o r o 1 + s r o c o 2 ( resistive load ) ? ` ` 2 4 v irms v o 1 s c o ( constant power load ) . the gain of the pwm modulator, g3, which includes the current loop, is simply: g3 = di lpk dv cspk = 1 r s where r s is the sense resistor connected be- tween the source of the external mosfet and ground (across which the l6561 reads the induc- tor current through pin 3). to calculate the transfer function g2 of the multi- plier block, one can consider that a variation d v comp , due to a line and/or load change, modi- fies the peak amplitude vcspk of the rectified sinusoid at the output of the multiplier. therefore: g2 = dv cspk dv comp = k m k p ? ` ` 2 v irms where k m is the gain of the multiplier and k p the partition ratio of the resistor divider that feeds a portion of the input voltage into pin 3. the electrical characteristics of the l6561 specify k m = 0.6 25% (@v comp = 4v, including temperature) but actually k m decreases for low values of v comp . in fig. 6 the typical value of k m is plotted against v comp along with the tolerance limits. since v comp gets lower when the mains voltage is high, this vari- ation of k m partly compensates for the increase of g2 with v irms , thus providing a mild voltage feedfor- ward effect. if one wants to take this non-linearity into account, he or she should linearise the large-signal multiplier gain in the neighborhood of the quiescent point of the error amplifier, so as to get the small-signal gain (km). please refer to [1] and the appendix for the relevant calculation technique. ultimately, the control-to-output transfer function will be: g ( s ) = dv o dv comp = g2 g3 g4 ( s ) = ? ? ? ? ? 1 4 km k p v 2 irms v o r o r s 1 1 + s r o c o 2 ( resistive load ) 1 2 km k p v 2 irms r s v o 1 s c o ( constant power load ) where the small-signal multiplier gain km could be assumed equal to k m for simplicity. 2.5 3 3.5 4 4.5 5 5.5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 vcomp km figure 6. plot of k m vs. e/a output AN1089 application note 4/12
from the above equations, it is apparent that the gain of the control-to-output function is strongly dependent on the input voltage, despite the slight compensation provided by k m . for design purpose, g(s) will have to be considered at the maximum mains voltage, where the gain is maximum and the loop bandwidth is maxi- mum as well. the feedback block is usually made up of a simple resistor divider (see fig. 7). only the upper resistor r7 is significant to the loop gain (the lower resistor r8 just sets the value of vo). it is then convenient to as- sume h=1 and to consider r7 as a part of the error amplifier block g1(s). error amplifier compensation in pfc preregulators that supply an electronic lamp ballast the error amplifier is compensated typically as shown in fig. 7 (see also ref. [2] and [3]). for this kind of load this circuit gives satisfactory results. it may not be acceptable, however, in other systems where stability must be ensured over a wide range of input voltage and load current, and does not work at all when the pfc preregulator supplies a switching converter. figure 8 shows the suggested compensation schemes for both the cases under consideration. with a resistive load the loop can be stabilised by adding a pole in the origin plus a low frequency zero that compensates the pole of the control-to-output gain (network a). ideally, this can give the desired bandwidth with 90 phase margin as well as high dc gain for good load regulation. with a constant power load the control-to-output gain has a pole in the origin thus the dc gain of the er- ror amplifier should be externally limited with a feedback resistor. if not, a second pole in the origin would be introduced, which would result in a system whose stability might be critical. limiting the gain goes to the detriment of preregulators load regulation but this has not a serious impact on the overall system since the downstream converter will easily compensate for that. the compensation network (b) adds a pole-zero couple that both makes the gain roll off at low frequency (so as to cross the 0 db axis at low frequency) and boosts the phase in the neighborhood of the cross- over frequency (so as to increase phase margin). the transfer functions of the compensation networks of fig. 8 a) and b) are respectively: g1 ( s ) = dv comp dv o = ? ? ? 1 + s c3 r11 s c3 r7 ( circuit a - resistive load ) r12 r7 1 + s c3 r11 1 + s c3 ( r11 + r12 ) ( circuit b - constant power load ) inv 2.5v e/a + _ l6561 c3 r7 to multiplier 2 1 r8 vo figure 7. typical compensation scheme in pfc preregulators for lamp ballast comp inv 2.5v e/a + _ l6561 c3 r12 r7 to mu ltip li er r11 2 1 r8 vo comp inv 2.5v e/a + _ l6561 c3 r7 to mu ltip lier r11 2 1 r8 vo a) resistive load b) constant power load figure 8. suggested compensation networks for tm boost pfc AN1089 application note 5/12
as a tool to ease the design of l6561s e/a compensation networks in tm boost pfc preregulators, the appendix contains a mathcad? file gathering the theory above illustrated and performing all the neces- sary calculations. conclusions this paper gets an insight into the control loop of tm controlled boost pfc preregulators based on the l6561 pfc controller. this reveals that the simple feedback capacitor used to compensate the error am- plifier in preregulators for lamp ballast may not be adequate in systems that may experience large vari- ations in input voltage and/or load current. moreover it leads to an unstable loop if the load is a switching converter. appropriate compensation schemes are suggested for both cases and a calculation tool (mathcad? file) is provided so as to make control loop design easier in such systems. references [1] "l6561, enhanced transition mode power factor corrector", (an966) [2] "l6569 - l6561 lighting application with pfc" (an991) [3] "electronic ballast with pfc using l6574 and l6561" (an993) [4] "design equations of high-power-factor flyback converters based on the l6561" (an1059) [5] "flyback converters with the l6561 pfc controller" (an1060) appendix this mathcad? file allows to design the control loop and performs a stability analysis of pfc preregula- tors in boost topology operated in transition mode and controlled by the l6561. highlighted equations indicate data that must be manually entered. these data are supposted to be known to the user as a result of the design of the pfc preregulator (the use of the pfc design software included in the cd-rom "linear and switching voltage regulators" is recommended). the example val- ues are taken from the l6561 demo board circuit. pfc converter data: output voltage v o := 400 v output capacitor c o := 47 m f sense resistor r s := 0.41 w output overvoltage threshold ovp := 40 v expected efficiency h := 0.9 multiplier biasing: input divider upper resistor r up := 1240 k w input divider lower resistor r low := 10 k w analysis setpoint: mains rms voltage v irms := 264 v output power p o := 80 w AN1089 application note 6/12
preliminary calculations & service variables: equivalent load resistance r o : = v o 2 p o r o = 2 10 3 w input divider gain kp : = r low r low + r up kp = 8 10 -3 large-signal multiplier gain: km(v comp ) := 0.651 (1 - 85.29 e -1.776 vcomp ) error amplifier quiescent point: v comp := 4 v comp : = root ? ? 2.5 + 2 p o r s h km ( v comp ) kp v irms 2 - v comp , v comp ? ? v comp = 2.898 [v] small signal multiplier gain km : = d dv comp [km ( v comp ) ( v comp - 2.5 ) ] km = 0.557 ------------------------------------------------------------------------------------------------------------------------------- ----------- j: = ? -1 n: = 100 dec: = 6 w:= 0,1..n w (w): = 10 w dec n - 1 f: = 1 control-to-output transfer function (constant power load): g (w) : = km kp v irms 2 2 v o 1 r s 10 6 j w c o compensated e/a transfer function (constant power load, refer to fig.8b) dc gain ( d v o / d v comp ): g o := 0.30 pole: p := 0.23 hz zero: z := 15 hz 0.1 1 10 100 1 . 10 3 50 0 50 100 150 |g| f db 0.1 1 10 100 1 . 10 3 91 90 89 /g f deg AN1089 application note 7/12
transfer function: g1 (w) : = g o 1 + j w 2 p z 1 + j w 2 p p open loop transfer function (constant power load): f( w ): = g ( w ) g1 ( w ) f f( w ): = arg (f( w )) 180 p crossover frequency: fc: = |root (|f(2 p f)| - 1, f)| fc = 18.836 hz phase margin: f : = 180 + f f (2 p fc) f = 52.167 0.1 1 10 100 1 . 10 3 60 40 20 0 |g1| f db 0.1 1 10 100 1 . 10 3 100 80 60 40 20 0 /g1 f deg 0.1 1 10 100 1 . 10 3 100 0 100 |f| f db 0.1 1 10 100 1 . 10 3 200 160 120 80 40 0 /f f deg AN1089 application note 8/12
feedback network implementation (constant power load, refer to fig. 8b): output divider upper resistor r7: = ovp 40 10 3 r7 = 1 10 3 k w output divider lower resistor r8: = 2.5 v o - 2.5 r7 r8 = 6.289 k w parallel feedback resistor: r12: = g o r7 r12 = 300 k w series feedback capacitor c3: = 10 6 2 p r12 ? ? 1 p 1 z ? ? c3 = 2.271 10 3 nf series feedback resistor r11: = 10 6 2 p z c3 r11 = 4.672 k w control-to-output transfer function (resistive load): g (w) : = km kp v irms 2 4 v o r o r s 1 1 + j w c o r o 2 10 - 6 pole location: p : = 10 6 p r o c o p = 3.386 hz 0.1 1 10 100 1 . 10 3 50 0 50 100 |g| f db 0.1 1 10 100 1 . 10 3 100 80 60 40 20 0 /g f deg AN1089 application note 9/12
compensated e/a transfer function (resistive load, refer to fig. 8a): high frequency gain: g h := 0.005 zero: z := 15 hz transfer function: g1 (w) : = g h 2 p z 1 + j w 2 p z j w open loop transfer function (resistive load) f( w ): = g( w ) g1( w ) f f( w ): = arg (f( w )) 180 p crossover frequency: fc: = |root (|f(2 p f )| - 1, f)| fc = 19.805 hz 0.1 1 10 100 1 . 10 3 100 50 0 50 100 |f| f db 0.1 1 10 100 1 . 10 3 200 160 120 80 40 0 /f f deg 0.1 1 10 100 1 . 10 3 60 40 20 0 20 |g1| f db 0.1 1 10 100 1 . 10 3 100 80 60 40 20 0 /g1 f deg AN1089 application note 10/12
phase margin: f : = 180 + f f (2 p fc) f = 62.563 feedback network implementation (resistive load, refer to fig. 8a): equivalent load resistance r7: = ovp 40 10 3 r7 = 1 10 3 k w output divider lower resistor r8: = 2.5 v o - 2.5 r7 r8 = 6.289 k w series feedback capacitor c3: = 10 6 2 p z gh r7 c3 = 2122 10 3 nf series feedback resistor r11: = 10 6 2 p z c3 r11 = 5 k w AN1089 application note 11/12
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the cons equences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com AN1089 application note 12/12

▲Up To Search▲

Price & Availability of AN1089

	To Download AN1089 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .